1. Field of the Invention
The present invention relates to a delay time generating circuit for use in an IC test system, and more particularly to a method of measuring a delay time which is carried out in calibrating a delay time generating circuit and a random pulse train generating circuit for use in such a method.
2. Description of the Related Art:
As shown in FIG. 1 of the accompanying drawings, a conventional delay time generating circuit 21 comprises n variable-delay circuits 22 whose delay time is established by binary data and n selectors 23 for selecting the respective variable-delay circuits 22. Each of the selectors 23 selects one of input signals supplied to its two respective terminals, e.g., a terminal A and a terminal B, in response to a selection control signal Sc transmitted from a controller (not shown), and outputs the selected the input signal from a terminal X thereof. The terminal A of each of the selectors 23 is supplied with an output signal directly from a preceding circuit, and the terminal B thereof is supplied with the same output signal through the corresponding variable-delay circuit 22. When the selectors 23 are selectively operated, corresponding variable-delay circuits 22 which have desired delay times, among all the n variable-delay circuits 22, are connected in series with each other, setting the entire delay time generating circuit 21 to a certain total delay time. The delay times of the variable-delay circuits 22 are determined by calibration data transmitted from the controller.
The delay time generating circuit 21 produces an output signal SO which is applied back to an input signal SIN thereof through a positive feedback loop comprising an AND gate 26, an OR gate 25, and a waveform shaper 24.
The AND gate 26 is supplied with a loop signal for turning on or off the positive feedback loop, as an input signal in addition to the output signal SO. The OR gate 25 is supplied with a start pulse for triggering the positive feedback loop to oscillate, as an input signal in addition to the output signal SO supplied as an output signal from the AND gate 26.
When a loop signal of a high level (logic "1") is supplied to the AND gate 26 and a single start pulse is supplied to the OR gate 25, an output signal SO of the delay time generating circuit 21 is applied to an input signal SIN thereof, causing the positive feedback loop to start to oscillate. Since the positive feedback loop oscillates at an oscillation period equal to the delay time of one cycle of the positive feedback loop, it is possible to determine the delay times of the variable-delay circuits 22 by determining the oscillation periods of output signals SO which are produced when the variable-delay circuits 22 are selected one at time, determining the oscillation period of an output signal SO which is produced when no variable-delay circuit 22 is selected, and calculating the differences between those oscillation periods. After the delay time of the variable-delay circuits 22 is determined, the loop signal is set to a low level (logic "0") to cause the positive feedback loop to stop oscillating. The variable-delay circuits 22 are calibrated based on the delay times that are thus determined.
With the above conventional method of measuring the delay times, however, if a periodic noise source such as a system clock is present close to the delay time generating circuit 21 and if the ratio between the period of the noise produced by the periodic noise source and the oscillation period of the positive feedback loop is close to an integer, then the positive feedback loop tends to oscillate unstably, resulting in a fluctuation in the oscillation period thereof. As a result, the delay times of the variable-delay circuits 22 cannot accurately be measured.